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vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com 10 a microbuck ? SIC402A/b integrated buck regulato r with programmable ldo description the vishay siliconix SIC402A/b an advanced stand-alone synchronous buck regulator featuring integrated power mosfets, bootstrap switch, and a programmable ldo in a space-saving powerpak mlp55-32l pin packages. the SIC402A/b are capable of operating with all ceramic solutions and switching frequencies up to 1 mhz. the programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. the internal ldo may be used to supply 5 v for the gate drive circuits or it may be bypassed with an external 5 v for optimum efficiency and used to drive external n-channel mosfets or other loads. additional feat ures include cycle-by-cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. the vishay siliconix SIC402A/b also provides an enable input and a power good output. features ? high efficiency > 95 % ? 10 a continuous output current capability ? integrated bootstrap switch ? programmable 200 ma ldo with bypass logic ? temperature compensated current limit ? pseudo fixed-frequency adaptive on-time control ? all ceramic solution enabled ? programmable input uvlo threshold ? independent enable pin for switcher and ldo ? selectable ultra-sonic power-save mode (SIC402A) ? selectable power-save mode (sic402b) ? programmable soft-start and soft-shutdown ? 1 % internal reference voltage ? power good output ? over-voltage and under-voltage protections ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? notebook, desktop, and server computers ? digital hdtv and digital consumer applications ? networking and telecommunication equipment ? printers, dsl, and stb applications ? embedded applications ? point of load power supplies typical application circuit and package options product summary input voltage range 3 v to 28 v output voltage range 0.6 v to 5.5 v operating frequency 200 khz to 1 mhz continuous output current 10 a peak efficiency 95 % package powerpak mlp55-32l typical application circuit for SIC402A/b (powerpak mlp55-32l) pad 1 a g n d lx pad 3 lx pad 2 v i n p g n d lx p g n d p g n d p g n d p g n d p g n d 17 1 8 19 20 21 t o n a g n d e n \ps v lx i lim p good bst v i n fbl a g n d v dd v out fb 1 2 3 4 5 7 6 8 ss p g n d v i n v i n v i n n c lx n c 9 10 11 12 13 14 15 16 24 lx 23 22 e n l v i n v out v out p good 3.3 v e n /ps v (tri-state) ldo_e n p g n d 31 30 29 25 26 27 2 8 32
www.vishay.com 2 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com pin configuration (top view) SIC402A/b pin configuration (top view) pad 1 a g n d lx pad 3 lx pad 2 v i n p g n d lx p g n d p g n d p g n d p g n d p g n d 17 1 8 19 20 21 t o n a g n d e n \ps v lx i lim p good bst v i n fbl a g n d v dd v out fb 1 2 3 4 5 7 6 8 ss p g n d v i n v i n v i n n c lx n c 9 10 11 12 13 14 15 16 p g n d 24 lx 23 22 e n l 31 30 29 25 26 27 2 8 32 pin description pin number symbol description 1fb feedback input for switching regulator used to pr ogram the output voltage - connect to an external resistor divider from v out to a gnd . 2v out switcher output voltage sense pin - also the input to the internal switch-over between v out and v ldo . the voltage at this pin must be less than or equal to the voltage at the v dd pin. 3v dd bias supply for the ic - when using the internal ldo as a bias power supply, v dd is the ldo output. when using an external power supply as the bias for the ic, the ldo output should be disabled. 4, 30, pad 1 a gnd analog ground 5fbl feedback input for the internal ldo - used to pr ogram the ldo output. connect to an external resistor divider from v dd to a gnd . 6, 9 to 11, pad 2 v in input supply voltage 7 ss the soft start ramp will be programmed by an inter nal current source chargi ng a capacitor on this pin. 8 bst bootstrap pin - connect a capacitor of at least 100 nf from bst to lx to develop the floating supply for the high-side gate drive. 12, 14 nc no connection 13 lxbst lx boost - connect to the bst capacitor. 23 to 25, pad 3 lx switching (phase) node 15 to 22 p gnd power ground 26 p good open-drain power good indi cator - high impedance indicates power is good. an external pull-up resistor is required. 27 i ilim current limit sense pin - used to program the current limit by connecti ng a resistor from i lim to lxs. 28 lxs lx sense - connects to r ilim 29 en/psv enable/power-save input for the sw itching regulator - connect to a gnd to disable the switching regulator, connect to v dd to operate with power-save mode and float to operate in forced continuous mode. 31 t on on-time programming input - set the on-time by connecting through a resistor to a gnd . 32 enl enable input for the ldo - connect enl to a gnd to disable the ldo. drive with logic signal for logic control, or program the v in uvlo with a resistor divider between v in , enl, and a gnd . ordering information part number package marking (line 1: p/n) SIC402Acd-t1-ge3 powerpak mlp55-32l SIC402A sic402bcd-t1-ge3 sic402b sic402db reference board format: line 1: dot line 2: p/n line 3: siliconix logo + lot code + esd symbol line 4: factory code + year code + work week code p/n fyww ii
document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 3 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com functional block diagram stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating/conditions for extended perio ds may affect device reliability. SIC402A/b functional block diagram absolute maximum ratings (t a = 25 c, unless otherwise noted) electrical parameter conditions limits unit v in to p gnd - 0.3 to + 30 v v in to v dd - 0.4 max. lx to p gnd - 0.3 to + 30 lx (transient < 100 ns) to p gnd - 2 to + 30 v dd to p gnd - 0.3 to + 6 en/psv, p good , ilim reference to p gnd - 0.3 to + (v dd + 0.3) t on to p gnd - 0.3 to + (v dd - 1.5) bst to lx - 0.3 to + 6 to p gnd - 0.3 to + 35 enl - 0.3 to v in a gnd to p gnd - 0.3 to + 0.3 temperature maximum junction temperature 150 c storage temperature - 65 to 150 power dissipation junction to ambient thermal impedance (r thja ) b ic section 50 c/w maximum power dissipation ambient temperature = 25 c 3.4 w ambient temperature = 100 c 1.3 esd protection hbm 2 kv nc nc
www.vishay.com 4 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com recommended operating range (all voltages referenced to gnd = 0 v) parameter min. typ. max. unit v in 328 v v dd to p gnd 35.5 v out 0.6 5.5 temperature operating junction temperature - 40 to 125 c recommended ambient temperature - 40 to 85 electrical specifications parameter symbol test conditions unless specified v in = 12 v, t a = + 25 c for typ., - 40 c to + 85 c for min. and max., t j = < 125 c, v dd = + 5 v, typical application circuit limits unit min. typ. max. input supplies input supply voltage v in 328 v v dd v dd 35.5 v in uvlo threshold a v uvlo sensed at enl pin, rising 2.4 2.6 2.95 sensed at enl pin, falling 2.23 2.4 2.57 v in uvlo hysteresis v uvlo, hys 0.25 v dd uvlo threshold v uvlo measured at v dd pin, rising 2.5 3 measured at v dd pin, falling 2.4 2.9 v dd uvlo hysteresis v uvlo, hys 0.2 v in supply current i in en/psv, enl = 0 v, v in = 28 v 10 20 a standby mode: enl = v dd , en/psv = 0 v 160 v dd supply current i dd en/psv, enl = 0 v 190 300 SIC402A, en/psv = v5v, no load (f sw = 25 khz), v fb > 0.6 v b 0.3 ma sic402b, en/psv = v5v, no load v fb > 0.6 v b 0.7 v dd = 5 v, f sw = 250 khz, en/psv = floating, no load b 8 v dd = 3 v, f sw = 250 khz, en/psv = floating, no load b 5 fb on-time threshold static v in and load 0.594 0.600 0.606 v frequency range f sw continuous mode operation 1000 khz minimum f sw , (SIC402A only) 25 bootstrap switch resistance 10 ? timing on-time t on continuous mode operation v in = 15 v, v out = 5 v, f sw = 300 khz, r ton = 133 k ? 999 1110 1220 ns minimum on-time b t on min. 80 minimum off-time b t off min. v dd = 5 v 250 v dd = 3 v 370 soft start soft start current b i ss 3a soft start voltage b v ss when v out reaches regulation 1.5 v analog inputs/outputs v out input resistance 500 k ? current sense zero-crossing detector threshold voltage lx-p gnd - 3 + 3 mv
document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 5 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com power good power good threshold voltage pg_v th_upper upper limit, v fb > internal 600 mv reference + 20 % pg_v th_lower lower limit, v fb < internal 600 mv reference - 10 start-up delay time (between pwm enable and p good high) pg_t d v dd = 5 v, c ss = 10 nf 12 ms v dd = 3 v, c ss = 10 nf 7 fault (noise-immunity) delay time b pg_i cc 5s leakage current pg_i lk 1a power good on-resistance pg_r ds-on 10 ? fault protection vally current limit c i lim v dd = 5 v, r ilim = 4460, t j = 0 c to + 125 c 8.5 10 11.5 a v dd = 3 v, r ilim = 4460 8.5 i lim source current 10 a i lim comparator offset voltage v ilm-lk with respect to a gnd - 10 0 + 10 mv output under-voltage fault v ouv_fault v fb with respect to internal 600 mv reference, 8 consecutive clocks - 25 % smart power-save protection threshold b p save_vth v fb with respect to internal 600 mv reference + 10 over-voltage protection threshold v fb with respect to internal 600 mv reference + 20 over-voltage fault delay b t ov-delay 5s over temperature shutdown b t shut 10 c hysteresis 150 c logic inputs/outputs logic input high voltage v ih 1 v logic input low voltage v il 0.4 en/psv input for p save operation b v dd = 5 v 2.2 5 en/psv input for forced continuous operation b 12 en/psv input for disabling switcher 00.4 en/psv input bias current i en en/psv = v dd or a gnd - 10 + 10 a enl input bias current enl = v in = 28 v 10 18 fbl, fb input bias current fbl_i lk fbl, fb = v dd or a gnd - 1 + 1 electrical specifications parameter symbol test conditions unless specified v in = 12 v, t a = + 25 c for typ., - 40 c to + 85 c for min. and max., t j = < 125 c, v dd = + 5 v, typical application circuit limits unit min. typ. max.
www.vishay.com 6 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com notes: a. v in uvlo is programmable using a resistor divider from v in to enl to a gnd . the enl voltage is compared to an internal reference. b. typical value measured on standard evaluation board. c. SIC402A/b has first order te mperature compensation for over current. re sults vary based upon the pcb thermal layout. d. the switch-over threshold is the maximum voltage differential between the v dd and v out pins which ensures that v ldo will internally switch-over to v out . the non-switch-over threshold is the mi nimum voltage differential between the v ldo and v out pins which ensures that v ldo will not switch-over to v out . e. the ldo drop out voltage is the voltage at which the ldo output drops 2 % below the nominal regulation point. linear dropout regulator fbl b v ldo acc 0.75 v ldo current limit ldo_i lim short-circuit protection, v in =12 v, v dd < 0.75 v 65 ma start-up and foldback, v in = 12 v, 0.75 < v dd < 90 % of final v dd value 115 operating current limit, v in = 12 v, v dd > 90 % of final v dd value 135 200 v ldo to v out switch-over threshold d v ldo-bps - 130 + 130 mv v ldo to v out non-switch-over threshold d v ldo-nbps - 500 + 500 v ldo to v out switch-over resistance r ldo v out = 5 v 2 ? ldo drop out voltage e from v in to v dd , v dd = + 5 v, i vldo = 100 ma 1.2 v electrical specifications parameter symbol test conditions unless specified v in = 12 v, t a = + 25 c for typ., - 40 c to + 85 c for min. and max., t j = < 125 c, v dd = + 5 v, typical application circuit limits unit min. typ. max.
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com electrical characteristics figure 1 - psm effiency - v in vs. load (v dd = 3.3 v, v out = 1.5 v) figure 2 - psm effiency - v in vs. load (v dd = 5 v, v out = 1.5 v) figure 3 - psm effiency - v in vs. load (v dd = 5 v, v out = 1.5 v) 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 e f f i c i e n c y ( % ) i o u t ( a ) v in = 5 v v in = 12 v 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 efficiency (%) i o u t ( a ) v in = 5 v v in = 12 v 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 e f f i c i e n c y ( % ) i o u t ( a ) v in = 5 v v in = 12 v v in = 18 v figure 4 - efficiency - psm vs. ccm (v dd = 3.3 v, v out = 1.5 v, v in = 12 v) figure 5 - efficiency - psm vs. ccm (v dd = 5 v, v out = 1.5 v, v in = 12 v) figure 6 - psm efficiency - v dd 3.3 v vs. 5 v (v out = 1.5 v, v in = 12 v) 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 efficiency (%) i o u t ( a ) psm ccm 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 efficiency (%) i o u t ( a ) psm ccm 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 0 1 2 3 4 5 6 7 8 9 10 efficiency (%) i o u t ( a ) v dd = 3.3 v v dd = 5 v
www.vishay.com 8 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com figure 7 - load regulation - fcm (v dd = 5 v, v out = 1.5 v) figure 8 - load regulation - psm (v dd = 5 v, v out = 1.5 v) figure 9 - switching frequency - psm vs. fcm (v dd = 5 v, v out = 1.5 v, v in = 12 v) v out o u t (v) ( v ) i out o u t (a) ( a ) 9 ,1 9 9 ,1 9 9 ,1 9 v out o u t (v) ( v ) i out o u t (a) ( a ) 9 ,1 9 9 ,1 9 9 ,1 9 0 50 100 150 200 250 300 350 400 0 1 2 3 4 5 6 7 8 9 1 0 f r e q u e n c y ( k h z ) fcm psm i o u t ( a ) figure 10 - load regulation - fcm (v dd = 3.3 v, v out = 1.5 v) figure 11 - load regulation - psm (v dd = 3.3 v, v out = 1.5 v) figure 12 - switching frequency - psm vs. fcm (v dd = 5 v, v in = 12 v) v out o u t (v) ( v ) i out o u t (a) ( a ) 9 ,1 9 9 ,1 9 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 012345678910 v out o u t (v) ( v ) i out o u t (a) ( a ) 9 ,1 9 9 ,1 9 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 1 0 v out = 5 v v out =3.3 v v out =2.5 v v out =1.5 v v out = 1 v e f f i c i e n c y ( % ) i o u t ( a )
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com figure 13 - start-up - en/psv (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a) figure 14 - start-up (pre-bias) - en/psv (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a) figure 15 - start-up (pre-bias) - en/psv (v dd = 5 v, v in = 1.5 v, i out = 0 a) figure 16 - shutdown - en/psv (v dd = 5 v, v in = 1.5 v, i out = 0 a) figure 17 - ultra-sonic psm - SIC402Acd (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a) figure 18 - forced continuous mode - SIC402Acd (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 10 a)
www.vishay.com 10 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com figure 19 - transient response - psm rising (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0.5 to 8.5 a, di/dt = 1 a/s) figure 20 - transient response - fcm (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 2.5 to 10 a, di/dt = 1 a/s) figure 21 - transient response - psm falling (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 8.5 to 0.5 a, di/dt = 1 a/s) figure 22 - thermal shutdown - 146 c (v in = 12 v, v out = 2.5 to 10 a, di/dt = 1 a/s)
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com operational description device overview the SIC402A/b is a step down synchronous dc/dc buck converter with integrated power mosfets and a 200 ma capable programmable ldo. the device is capable of 10 a operation at very high efficiency. a space saving 5 x 5 (mm) 32-pin package is used. the programmable operating frequency of up to 1 mhz enables optimizing the configuration for pcb area and efficiency. the buck controller uses a pseudo-fixed frequency adaptive on-time control. this contro l method allows fast transient response which permits the us e of smaller output capacitors. input voltage requirements the SIC402A/b requires two input supplies for normal operation: v in and v dd . v in operates over a wide range from 3 v to 28 v. v dd requires a 3 v to 5.5 v supply input that can be an external source or the internal ldo configured to supply 3 v to 5.5 v from v in . power up sequence when the SIC402A/b uses an external power source at the v dd pin, the switching regulato r initiates the start up when v in , v dd and en/psv are above thei r respective thresholds. when en/psv is at logic high, v dd needs to be applied after v in rises. it is also recommended to use a 10 ? resistor between an external power source and the v dd pin. to start up by using the en/psv pin when both v dd and v in are above their respective thresh olds, apply en/psv to enable the start-up process. for SIC402A/b in self-biased mode, refer to the ldo section for a full description. shutdown the SIC402A/b can be shut-down by pulling either v dd or en/psv below its threshold. when using an external power source, it is recommended that the v dd voltage ramps down before the v in voltage. when v dd is active and en/psv at logic low, the output voltage discharges into the v out pin through an internal fet. pseudo-fixed frequency ad aptive on-time control the pwm control method used for the SIC402A/b is pseudo-fixed frequency, adaptive on-time, as shown in figure 23. the ripple voltage generated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trigger the on -time of the controller. the adaptive on-time is determined by an internal one-shot timer. when the one-shot is tri ggered by the output ripple, the device sends a single on-time pulse to the highside mosfet. the pulse period is determined by v out and v in ; the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time arrangement, the device auto matically anticipates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the advantages of adaptive on-time control are: ? predictable operating frequency compared to other variable frequency methods. ? reduced component count by eliminating the error amplifier and compensation components. ? reduced component count by removing the need to sense and control inductor current. ? fast transient response - the response time is controlled by a fast comparator instead of a typically slow error amplifier. ? reduced output capacitance due to fast transient response. one-shot timer and operating frequency the one-shot timer operates as shown in figure 24. the fb comparator output goes high when v fb is less than the internal 600 mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal comparator and a capacitor. one comparator input is connected to v out , the other input is connected to the capacitor. when the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns off. figure 23 - pwm control method, v out ripple v i n c i n v lx q1 q2 l esr + fb v lx t o n v fb c out v out fb threshold
www.vishay.com 12 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com this method automatically pr oduces an on-time that is proportional to v out and inversely proportional to v in . under steady-state conditions, th e switching frequency can be determined from the on-time by the following equation. the SIC402A/b uses an external resistor to set the on-time which indirectly sets the frequency. the on-time can be programmed to provide an operating frequency up to 1 mhz using a resistor between the t on pin and ground. the resistor value is selected by the following equation. the constant, k, equals 1, when v dd is greater than 3.6 v. if v dd is less than 3.6 v and v in is greater than (v dd - 1.75) x 10, k is shown by the following equation. the maximum r ton value allowed is shown by the following equation. v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 600 mv reference voltage, see figure 25. note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc output voltage v out is offset by the output ripple according to the following equation. when a large capacitor is placed in parallel with r 1 (c top ) v out is shown by the following equation. enable and power-save inputs the en/psv input is used to ena ble or disable the switching regulator. when en/psv is low (grounded), the switching regulator is off and in its lowest power state. when off, the output of the switching regul ator soft-discharges the output into a 500 k ? internal resistor via the v out pin. when en/psv is allowed to float, the pin voltage will float to 33 % of the voltage at v dd . the switching regulator turns on with power-save disabled and all switching is in forced continuous mode. when en/psv is high (above 44 % of the voltage at v dd ), the switching regulator turns on with power-save enabled. the SIC402A/b p save operation reduces the switching frequency according to the load for increased efficiency at light load conditions. forced continuous mode operation the SIC402A/b operates the switcher in fcm (forced continuous mode) by floati ng the en/psv pin (see figure 26). in this mode one of t he power mosfets is always on, with no intentional dead time other than to avoid cross-conduction. this feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switching of the mosfets. dh is gate signal to drive upper mosfet. dl is lower gate signal to drive lower mosfet. figure 24 - on-time generation figure 25 - output voltage selection fb v rep - + v out v i n r ton on-time = k x r ton x ( v out/ v i n ) fb comparator one-shot timer gate dri v es dh dl q1 q2 l q1 esr fb v out c out v lx + v in f s w = v out t o n x v i n r ton = k 25 pf x f sw k = (v dd - 1.75) x 10 v in r ton_max. = v i n _mi n . 15 a v out r 1 r 2 to fb pin v out = 0.6 x 1 + + r 1 r 2 2 v ripple figure 26 - forced continuous mode operation v out = 0.6 x 1 + + x r 1 r 2 2 v ripple 1 + (r 1 c top ) 2 1 + c top r 2 x r 1 r 2 + r 1 2 fb ripple v oltage ( v fb ) ind u ctor c u rrent dc load c u rrent fb threshold dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold dl dri v es high w hen on-time is completed. dl remains high u ntil v fb falls to the fb threshold.
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com ultrasonic power-sa ve operation (SIC402A) the SIC402A provides ultras onic power-save operation at light loads, with the minimum operating frequency fixed at slightly under 25 khz. this is accomplished by using an internal timer that monitors the time between consecutive high-side gate pulses. if the time exceeds 40 s, dl drives high to turn the low-side mosfet on. this draws current from v out through the inductor, forcing both v out and v fb to fall. when v fb drops to the 600 mv threshold, the next dh (the drive signal for the high side fet) on-time is triggered. after the on-time is completed the high-side mosfet is turned off and the low-side mo sfet turns on. the low-side mosfet remains on until the inductor current ramps down to zero, at which point the lo w-side mosfet is turned off. because the on-times are forced to occur at intervals no greater than 40 s, the frequency will not fall far below 25 khz. figure 27 shows ultrasonic power-save operation. power-save operation (sic402b) the sic402b provides power-s ave operation at light loads with no minimum operating frequency. with power-save enabled, the internal zero crossing comparator monitors the inductor current via the voltage across the low-side mosfet during the off-time. if the inductor current falls to zero for 8 consecutive switching cycles, the controller enters mosfet on each subsequent cycle prov ided that the power-save operation. it will turn off the low-side mosfet on each subsequent cycle provided that the current crosses zero. at this time both mosfets remain off until v fb drops to the 600 mv threshold. because the mosfets are off, the load is supplied by the output capacitor. if the inductor current does not reach zero on any switching cycle, the controller immedi ately exits power-save and returns to forced continuous mode. figure 28 shows power-save operation at light loads smart power-save protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with power-save enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shut-down. smart power-save prevents this cond ition. when the fb voltage exceeds 10 % above nominal, the device immediately disables power-save, and dl drives high to turn on the low-side mosfet. this draws current from v out through the inductor and causes v out to fall. when v fb drops back to the 600 mv trip point, a normal t on switching cycle begins. this method prevents a hard ovp shut-down and also cycles energy from v out back to v in . it also minimizes operating power by avoiding forced conduction mode operation. figure 29 shows typical waveforms for the smart power-save feature. figure 27 - ultrasonic power-save operation fb ripple v oltage ( v fb ) ind u ctor c u rrent (0 a) fb threshold (600 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold after the 40 s time-o u t, dl dri v es high if v fb has not reached the fb threshold. minim u m f s w ~ 25 khz 40 s time-out figure 28 - power-sae ode figure 29 - smart power-sae v out drifts u p to d u e to leakage c u rrent flo w ing into c out smart po w er sa v e threshold fb threshold dh and dl off high-side dri v e (dh) lo w -side dri v e (dl) n ormal v out ripple v out discharges v ia ind u ctor and lo w -side mosfet single dh on-time p u lse after dl t u rn-off n ormal dl p u lse after dh on-time p u lse dl t u rns on w hen smart psa v e threshold is reached dl t u rns off fb threshold is reached
www.vishay.com 14 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com smartdrive tm for each dh pulse the dh driver initially turns on the high side mosfet at a lower speed, allowing a softer, smooth turn-off of the low-side diode. once the diode is off and the lx voltage has risen 0.5 v above p gnd , the smartdrive circuit automatically drives th e high-side mosfet on at a rapid rate. this technique reduces switching losses while maintaining high efficiency and also avoids the need for snubbers for the power mosfets. current limit protection the device features programma ble current limiting, which is accomplished by using the r ds(on) of the lower mosfet for current sensing. the current limit is set by r ilim resistor. the r ilim resistor connects from the i lim pin to the lxs pin which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~ 10 a current flows from the i lim pin and through the r ilim resistor, creating a voltage drop across the resistor. while the low-side mosfet is on, the inductor current flows through it and creates a voltage across the r ds(on) . the voltage across the mosfet is negative with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the i lim pin will be negative and current lim it will activate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the i lim voltage back up to zero. this method regulates the inductor valley current at the level shown by i lim in figure 30. setting the valley current limit to 10 a results in a peak inductor current of 10 a plus peak ripple current. in this situation, the average (load) current through the inductor is 10 a plus one-half the peak-to-peak ripple current. the internal 10 a current source is temperature compensated at 4100 ppm in or der to provide tracking with the r ds(on) . the r ilim value is calculated by the following equation. r ilim = 446 x i lim x [0.099 x (5 v - v dd ) + 1] when selecting a value for r ilim be sure not to exceed the absolute maximum volt age value for the i lim pin. note that because the low-side mosfet with low r ds(on) is used for current sensing, the pcb layout, solder connections, and pcb connection to the lx node must be done carefully to obtain good results. r ilim should be connected directly to lxs (pin 28). soft-start of pwm regulator SIC402A/b has a programmable soft-start time that is controlled by an external capac itor at the ss pin. after the controller meets both uvlo and en/psv thresholds, the controller has an internal current source of 3 a flowing through the ss pin to charge the capacitor. during the start up process (figure 31), 50 % of the voltage at the ss pin is used as the reference for the fb comparator. the pwm comparator issues an on-time pulse when the voltage at the fb pin is less than 40 % of the ss pin. as a result, the output voltage follows the ss voltage. the output voltage reaches and maintains regulation when the soft start voltage is ? 1.5 v. the time between the first lx pulse and v out reaching regulation is the soft-start time (t ss ). the calculation for the soft-start time is shown by the following equation. the voltage at the ss pin continues to ramp up and eventually equals 64 % of v dd . after the soft start completes, the fb pin voltage is compared to an internal reference of 0.6 v. the delay time between the v out regulation point and p good going high is shown by the following equation. pre-bias startup the SIC402A/b can start up normally even when there is an existing output voltage pr esent. the soft start time is still the same as normal start up (when the output voltage starts from zero). the output voltage starts to ramp up when 40 % of the voltage at ss pin meets the existing fb voltage level. pre-bias startup is achieved by turning off the lower gate when the inductor current falls below zero. this method prevents the output vo ltage from discharging. figure 30 - valley current limit i peak i load i lim ind u ctor c u rrent figure 31 - soft-start timing diagram t ss = c ss x 1.5 v 3 a t pgood-delay = c ss x (0.64 x v dd - 1.5 v) 3 a
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 15 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com power good output the p good (power good) output is an open-drain output which requires a pull-up resist or. when the voltage at the fb pin is 10 % below the nominal voltage, p good is pulled low. it is held low until the output voltage returns above - 8 % of nominal. p good will transition low if the v fb pin exceeds + 20 % of nominal, which is also the over-voltage shutdown threshold. p good also pulls low if the en/psv pin is low when v dd is present. output over-vol tage protection over-voltage protection becomes active as soon as the device is enabled. the threshold is set at 600 mv + 20 % (720 mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controll er remains off, until the en/psv input is toggled or v dd is cycled. there is a 5 s delay built into the ovp detector to prevent false transitions. p good is also low after an ovp event. output under-voltage protection when v fb falls 25 % below its nominal voltage (falls to 450 mv) for eight consecutive clock cycles, the switcher is shut off and the dh and dl drives are pulled low to tri-state the mosfets. the controller stays off until en/psv is toggled or v dd is cycled. v dd uvlo, and por uvlo (under-voltage lock-out) circuitry inhibits switching and tri-states the dh/dl drivers until v dd rises above 3 v. an internal por (power-on reset) occurs when v dd exceeds 3 v, which resets the fault latc h and a soft-sta rt counter cycle begins which prepares for soft-start. the SIC402A/b then begins a soft-start cycle. the pwm will shut off if v dd falls below 2.4 v. ldo regulator SIC402A/b has an option to bi as the switcher by using an internal ldo from v in . the ldo output is connected to v dd internally. the output of the ldo is programmable by using external resistors from the v dd pin to a gnd (see figure 32). the feedback pin (fbl) for the ldo is regulated to 750 mv. the ldo output voltage is set by the following equation. a minimum capacitance of 1 f referenced to a gnd is normally required at the output of the ldo for stability. note that if the ldo voltage is set lower than 4.5 v, the minimum output capacitance for the ldo is 10 f. ldo enl functions the enl input is used to enable/disable the internal ldo. when enl is a logic low, the ldo is off. when enl is above the v in uvlo threshold, the ldo is enabled and the switcher is also enab led if the en/psv and v dd are above their threshold. the table be low summarizes the function of enl and en/psv pins. the enl pin also acts as the switcher under-voltage lockout for the v in supply. when SIC402A/b is self-biased from the ldo and runs from the v in power source only, the v in uvlo feature can be used to prevent false uv faults for the pwm output by programming with a resistor divider at the v in , enl and a gnd pins. when SIC402A/b has an external bias voltage at v dd and the enl pin is used to program the v in uvlo feature, the voltage at fbl needs to be higher than 750 mv to force the ldo off. timing is important when driving enl with logic and not implementing v in uvlo . the enl pin must transition from high to low within 2 switching cycles to avoid the pwm output turning off. if enl goes below the v in uvlo threshold and stays above 1 v, then the swit cher will turn off but the ldo will remain on. ldo start-up before start-up, the ldo checks the status of the following signals to ensure proper operation can be maintained. 1. enl pin 2. v in input voltage when the enl pin is high and v in is above the uvlo point, the ldo will begin start-up. duri ng the initial phase, when the v dd voltage (which is the ldo output voltage) is less than 0.75 v, the ldo initiates a current-limited start-up (typically 65 ma) to charge the output c apacitors while protecting from a short circuit event. when v dd is greater than 0.75 v but still less than 90 % of its final value (as sensed at the fbl pin), the ldo current limit is in creased to ~ 115 ma. when v dd has reached 90 % of the final value (as sensed at the fbl pin), the ldo current limit is increased to ~ 200 ma and the ldo output is quickly driven to the nominal value by the internal ldo regulator. it is recommended that during ldo figure 32 - ldo output voltage selection v dd r ldo1 to fbl pin r ldo2 v ldo = 750 mv x 1 + r ldo1 r ldo2 en/psv enl ldo switcher disabled low, < 0.4 v off off enabled low, < 0.4 v off on disabled 1 v < high < 2.6 v on off enabled 1 v < high < 2.6 v on off disabled high, > 2.6 v on off enabled high, > 2.6 v on on
www.vishay.com 16 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com start-up to hold the pwm switching off until the ldo has reached 90 % of the final value. this prevents overloading the current-limited ldo output during the ldo start-up. due to the initial current limit ations on the ldo during power up (figure 33), any exter nal load attached to the v dd pin must be limited to less than the st art up current before the ldo has reached 90 % of its final regulation value. ldo switch-over operation the SIC402A/b includes a swit ch-over function for the ldo. the switch-over function is designed to increase efficiency by using the more efficient dc/dc converter to power the ldo output, avoiding the less efficient ldo regulator when possible. the switch-over function connects the v dd pin directly to the v out pin using an internal switch. when the switch-over is complete the ldo is turned off, which results in a power savings and maxi mizes efficiency. if the ldo output is used to bias the s ic402a/b, then after switch-over the device is self-powered from the switching regulator with the ldo turned off. the switch-over starts 32 switching cycles after p good output goes high. the voltages at the v dd and v out pins are then compared; if the two voltages are within 300 mv of each other, the v dd pin connects to the v out pin using an internal switch, and the ldo is turned off. to avoid unwanted switch-over, the minimum difference between the voltages for v out and v dd should be 500 mv. it is not recommended to use the switch-over feature for an output voltage less than v dd uvlo threshold since the SIC402A/b is not operational below that threshold. switch-over mosfet parasitic diodes the switch-over mosfet contai ns parasitic diodes that are inherent to its construction, as shown in figure 34. if the voltage at the v out pin is higher than v dd , then the respective diode will turn on and the current will flow through this diode. this has the potential of damaging the device. therefore, v out must be less than v dd to prevent damaging the device. design procedure when designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specified. the maximum input voltage (v in max. ) is the highest specified input voltage. the minimum input voltage (v in min. ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters define the design. ? nominal output voltage (v out ) ? static or dc output tolerance ? transient response ? maximum load current (i out ). there are two values of load current to evaluate - continuous load current and peak load current. continuous load current relates to thermal stresses whic h drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design. v in = 12 v 10 % v out = 1.5 v 4 % f sw = 300 khz load = 10 a maximum frequency selection selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. the desired switching frequency is 300 khz which results from using components selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. to select r ton , use the maximum value for v in , and for t on use the value associated with maximum v in . figure 33 - ldo start-up figure 34 - switch-over mosfet parasitic diodes v out parastic diode s w itcho v er mosfet s w itcho v er control v dd ldo r ton = k 25 pf x f sw
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 17 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com substituting for r ton results in the fo llowing solution. r ton = 133.3 k ? , use r ton = 130 k ? inductor selection in order to determine the indu ctance, the ripple current must first be defined. low inductor values result in smaller size but create higher ripple current which can reduce efficiency. higher inductor values will r educe the ripple current/voltage and for a given dc resistance are more efficient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efficiency are all used in the selection process. the ripple current will also set the boundary for p save operation. the switching will typically enter p save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4 a then p save operation will typically start for loads less than 2 a. if ripple current is set at 40 % of maximum lo ad current, then p save will start for loads less than 20 % of maximum current. the inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. this provides an optimal trade-off between cost, efficiency, and transient performance. during the on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. example in this example, the inductor ripple current is set equal to 45 % of the maximum load current. therefore ripple current will be 45 % x 10 a or 4.5 a. to find the minimum inductance needed, use the v in and t on values that correspond to v inmax . a slightly larger value of 1 h is selected. this will decrease the maximum i ripple to 4.43 a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. capacitor selection the output capacitors are chosen based upon required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output rippl e plus 1/2 of the peak-to-peak ripple. a change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal for output voltage ripple is 3 % of 1.5 v or 45 mv. the maximum esr value allowed is shown by the following equations. the output capacitance is usual ly chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1 s), the output capacitor must absorb all the inductor's stored energy. this will cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.65 v (150 mv rise upon load release), and a 10 a load release, the required capacitance is shown by the next equation. during the load release time, the voltage cross the inductor is approximately - v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the di/dt of the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor; therefore a smaller capacitance can be used. the following can be used to calculate the needed capacitance for a given di load /dt. peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 10 + 1/2 x 4.43 = 12.215 a i max. = maximum load release = 10 a t o n = v out v i n max. x f s w l = ( v i n - v out ) x t o n i ripple l = (13.2 - 1.5) x 379 ns 4.5 a = 0.99 h t o n _ v i n mi n = 25 pf x r to n x v out v i n mi n i ripple = ( v i n - v out ) x t o n l i ripple_ v i n mi n = (10. 8 - 1.5) x 451 ns 1 h = 451 ns = 4.19 a esr a = v ripple i ripplemax esr max = 10.2 m = 45 m v 4.43 a c out_mi n = l (i out + x i ripplemax ) 2 ( v peak ) 2 - ( v out ) 2 1 2 c out_mi n = 1 h (10 + x 4.43) 2 (1.65) 2 - (1.5) 2 c out_mi n = 316 f 1 2 rate of change of load current = di load d t
www.vishay.com 18 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com example this would cause the output current to move from 10 a to 0 a in 4 s, giving the minimum output capacitance requirement shown in the following equation. note that c out is much smaller in this example, 169 f compared to 316 f based on a worst-case load release. to meet the two design criteria of minimum 316 f and maximum 10.2 m ? esr, select one capacitor of 330 f and 9 m ? esr. stability considerations unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple vo ltage is too low. this causes the fb comparator to trigger prematurely after the 250 ns minimum off-time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple volt age at the output, but in most applications it will not affect op eration. this form of instability can usually be avoided by prov iding the fb pin with a smooth, clean ripple signal that is at least 10 mv p-p , which may dictate the need to increase the esr of t he output capacitors. it is also imperative to provide a proper pcb layout as discussed in the layout guidelines section. another way to eliminate doubling-pulsing is to add a small (~ 10 pf) capacitor across the upper feedback resistor, as shown in figure 35. this capacitor should be left unpopulated until it can be confirmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional connection on the pcb should be available for this capacitor. esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for ch ecking stability is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide 10 mv p-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insufficient esr. the on-time control regu lates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and discharging during the switching cycle. for most applications the minimum esr ripple voltage is dominated by t he output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching frequency. the formula for minimum esr is shown by the following equation. using ceramic output capacitors when the system is using high esr value capacitors, the feedback voltage ripple lags the phase node voltage by 90 . therefore, the converter is ea sily stabilized. when the system is using ceramic output capacitors, the esr value is normally too small to meet the above es r criteria. as a result, the feedback voltage ripple is 180 from the phase node and behaves in an unstable manner. in this application it is necessary to add a small virtual esr network that is composed of two capacitors and one resistor, as shown in figure 36. c out = i lpk x l x - x dt 2 ( v pk - v out ) i lpk v out i max dl load dl load dt = 2.5 a 1 s c out = 12.215 x 1 h x - x 1 s 2 (1.65 - 1.5) 12.215 1.5 10 2.5 c out = 169 f figure 35 - capacitor coupling to fb pin v out r 1 r 2 to fb pin c top esr mi n = 3 2 x x c out x f s w
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 19 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com the ripple voltage at fb is a superposition of two voltage sources: the voltage across c l and output ripple voltage. they are defined in the following equations. figure 37 shows the magnitude of the ripple contribution due to c l at the fb pin. it is shown by the following equation. figure 38 shows the magnitude of the ripple contribution due to the output voltage ripple at the fb pin. it is shown by the following equation. the purpose of this network is to couple the inductor current ripple information into the feedback voltage such that the feedback voltage has 90 phase lag to the switching node similar to the case of usin g standard high esr capacitors. this is illustrated in figure 39. the magnitude of the feedba ck ripple voltage, which is dominated by the contribution from c l , is controlled by the value of r 1 , r 2 and c c . if the corner frequency of (r 1 //r 2 ) x c c is too high, the ripple magnitude at the fb pin will be smaller, which can lead to double-pulsing. conversely, if the corner frequency of (r 1 //r 2 ) x c c is too low, the ripple magnitude at fb pin will be higher. since the SIC402A/b regulates to the valley of the ri pple voltage at the fb pin, a high ripple magnitude is undesirable as it significantly impacts the output voltage regulation. as a result, it is desirable to select a corner frequency for (r 1 //r 2 ) x c c to achieve enough, but not excessive, ripple magnitude and phase margin. the component values for r 1 , r 2 , and c c should be calculated using the following procedure. select c l (typical 10 nf) and r l to match with l and dcr time constant using the following equation. figure 36 - virtual esr ramp circuit figure 37 - fb voltage by c l voltage i l x dcr (s x l/dcr + 1) s x r l c l + 1 v cl = i l 8c x f sw v out = (r 1 //r 2 ) x s x c c (r 1 //r 2 ) x s x c c + 1 vfb cl = v cl x figure 38 - fb voltage by output voltage figure 39 - fb voltage in phasor diagram vfb v out = v out x r 2 r 1 // + r 2 1 s x c c dcr x c l r l = l
www.vishay.com 20 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com select c c by using the following equation. the resistor values (r 1 and r 2 ) in the voltage divider circuit set the v out for the switcher. the typical value for c c is from 10 pf to 1 nf. dropout performance the output voltage adjustme nt range for continuous conduction operation is limited by the fixed 250 ns (typical) minimum off-time of the one-shot. when working with low input voltages, the duty-factor limit mu st be calculated using worst- case values for on- and off-times. the duty-factor limitation is shown by the next equation. the inductor resistance and mosfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors affect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator offset is trimmed so that under static conditions it trips when the feedback pin is 600 mv, 1 %. the on-time pulse from the SIC402A/b in the design example is calculated to give a pseudo-fixed frequency of 300 khz. some frequency variation with line and load is expected. this variation changes the output ri pple voltage. because adaptive on-time converters regulate to th e valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the output ripple is 50 mv with v in = 6 v, then the measured dc output will be 25 mv above the comparator trip point. if the ripple increases to 80 mv with v in = 25 v, then the measured dc output will be 40 mv above the comparator trip. the best way to minimize this effect is to minimize the output ripple. the use of 1 % feedback resistors may result in up to 1 % error. if tighter dc accuracy is required, 0.1 % resistors should be used. the output inductor value may change with current. this will change the output ripple and th erefore will have a minor effect on the dc output voltage. the output esr also affects the output ripple and thus has a minor effect on the dc output voltage. switching frequency variation the switching frequency varies with load current as a result of the power losses in the mosfets and dcr of the inductor. for a conventional pwm constant-frequency converter, as load increases the duty cycle also increases slightly to compensate for ir and switchin g losses in the mosfets and inductor. an adaptive on-time converter must also compensate for the same losses by increa sing the effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essentially constant for a given v out /v in combination, to offset th e losses the off-time will tend to reduce slightly as load increases. the net effect is that switching frequency increases slightly with increasing load. c c r 1 //r 2 13 2 x x f sw x duty = t o n (mi n ) t o n (mi n ) x t off(max)
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 21 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com sic402b evaluation board schematic figure 40 - evaluation board schematic ton lxbst soft lx vo bst pgd ilim fbl en_psv vdd vout fb vin vdd p8 vin p8 vin 1 + c17 330uf + c17 330uf + c10 10uf + c10 10uf r15 10k r15 10k r8 4.64k r8 4.64k b4 vo_gnd b4 vo_gnd 1 p1 vdd p1 vdd 1 r39 0r r39 0r + c18 330uf + c18 330uf c30 68pf c30 68pf + c22 10uf + c22 10uf c26 1uf c26 1uf r23 6.81k r23 6.81k p10 vout p10 vout 1 c6 1uf c6 1uf + c16 330uf + c16 330uf p11 vo_gnd p11 vo_gnd 1 + c20 10uf + c20 10uf r10 10k r10 10k c29 3.3nf c29 3.3nf u1 sic401/2/3 u1 sic401/2/3 fb 1 fbl 5 vdd 3 agnd 30 vout 2 vin 6 soft 7 bst 8 vin 9 vin 10 vin 11 nc 14 lx 23 nc 12 pgnd 22 pgnd 21 lx 25 lx 24 pgnd 20 pgnd 19 pgnd 18 pgnd 17 pgnd 16 pgnd 15 enl 32 ton 31 agnd 35 en/psv 29 lxbst 13 ilim 27 pgd 26 lxs 28 lx 33 vin 34 agnd 4 p7 pgood p7 pgood 1 b2 vin_gnd b2 vin_gnd 1 p9 vin_gnd p9 vin_gnd 1 r7 0r r7 0r c27 1uf c27 1uf r30 130k r30 130k r14 0 r14 0 r13 100 r13 100 l1 1uh l1 1uh + c12 150uf + c12 150uf b3 vo b3 vo 1 c15 33uf c15 33uf r52 0 r52 0 p2 en_psv p2 en_psv 1 c25 68pf c25 68pf b1 vin b1 vin 1
www.vishay.com 22 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com bill of materials item qty. reference designator pcb footprint material value voltage description vendor p/n 1 1 c12 radial 150 f 35 v cap, radial 150 f 35 v eu-fm1v151 2 3 c10, c20, c22 sm1210 x5r 10 f 25 v cap10 f 25 v 1210 tmk325bj106mm 3 3 c26, c27, c6 sm0805 x7r 1 f 35 v cap cer 1 f 35 v x7r 0805 gmk212b7105kg-t 4 2 c30, c25 sm0402 x7r 68 pf 50 v cap, 68 pf, 50 v, 0402 vj0402y680kxacw1bc 5 1 c15 sm0805 x7r 33 f 10 v 33 f 10 v 0805 lmk212bj336mg-t 6 3 c16, c17, c18 case d x7r 33 f 6.3 v 33 f 6.3 v solid tantalum surface mount 293d337xd6r3d2 7 1 c29 sm0603 x7r 3.3 nf 50 v cap, 3.3 nf 50 v vj0603y332kxacw1bc 8 4 r52, r7, r14, r39 sm0603 0 ? 50 v res 0 ? 1% generic 9 1 r30 sm0603 130 k ? 50 v res 130 k ? 1% generic 10 1 r15 sm0603 10 k ? 50 v res 10 k ? 1% generic 11 1 r13 sm0603 100 ? 50 v res 100 ? 1% generic 12 1 r8 sm0603 4.64 k ? 50 v res 4.64 k ? 1% generic 13 1 r23 sm0603 6.81 k ? 50 v res 6.81 k ? 1% generic 14 1 r10 sm0603 10 k ? 50 v res 10 k ? 1% generic 15 1 u1 powerpak mlp55-32l sic402b 10 a microbuck ? SIC402A/b integarted buck regulator with programmable ldo sic402bcd 16 4 b1, b2, b3, b4 connector 17 1 l1 ihlp4040 1 h 1 h ihlp4040dzer1r0m01
vishay siliconix SIC402A, sic402bcd document number: 63729 s12-2109-rev. b, 03-sep-12 www.vishay.com 23 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com pcb layout of the evaluation board figure 41 - top layer figure 43 - middle layer 2 figure 45 - top component figure 42 - middle layer 1 figure 44 - bottom layer figure 46 - bottom component
www.vishay.com 24 document number: 63729 s12-2109-rev. b, 03-sep-12 vishay siliconix SIC402A, sic402bcd this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com package dimensions and marking info note: 1. use millimeters as the primary measurement. 2. dimensioning and tolerances conform to asme y1 4.5m - 1994. 3. n is the number of terminals nd is the number of terminals in x-direction and ne is the number of terminals in y-direction. 4. dimensions applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of the package by using indent ation mark or other feature of package b ody. 6. exact shape and size of this feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals. vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63729 . dime nsion s millimeters inches note min. nom. max. min. nom. max. a 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.00 - 0.002 8 a2 0.20 ref. 0.008 ref. b 0.20 0.25 0.30 0.078 0.098 0.110 4 d 5.00 bsc 0.196 bsc e 0.50 bsc 0.019 bsc e 5.00 bsc 0.196 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n32 323 nd 8 8 3 ne 8 8 3 dimen sions millimeters inches min. nom. max. min. nom. max. d2-1 3.43 3.48 3.53 0.135 0.137 0.139 d2-2 1.00 1.05 1.10 0.039 0.041 0.043 d2-3 1.00 1.05 1.10 0.039 0.041 0.043 d2-4 1.92 1.97 2.02 0.075 0.077 0.079 d2-5 0.36 0.014 e2-1 3.43 3.48 3.53 0.135 0.137 0.139 e2-2 1.61 1.66 1.71 0.063 0.065 0.067 e2-3 1.43 1.48 1.53 0.056 0.058 0.060 e2-4 0.45 0.018
document number: 64714 www.vishay.com revision: 29-dec-08 1 package information vishay siliconix powerpak ? mlp55-32l case outline notes 1. use millimeters as the primary measurement. 2. dimensioning and tolerances conform to asme y14.5m. - 1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction. 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of the package by using i ndentation mark or other feature of package body. 6. exact shape and size of this feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals. b y marking e pin 1 dot top v ie w d (5 mm x 5 mm) 32l t/slp e2 - 2 ( n d-1) xe ref. bottom v ie w side v ie w d2 - 1 r0.200 pin #1 identification b e d2 - 4 d2 - 3 e2 - 3 d4 9 24 25 32 a 0.10 c b 2x 0.0 8 c c a a2 a1 b ( n d-1) xe ref. l 0.36 0.360 5 6 0.10 c a b 4 d2 - 2 e2 - 1 0.10 c a 2x 8 17 16 0.45 1 millimeters inches dim min. nom. max. min. nom. max. a 0.80 0.85 0.90 0.031 0.033 0.035 a1 (8) 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 5.00 bsc 0.196 bsc e 0.50 bsc 0.019 bsc e 5.00 bsc 0.196 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 32 32 nd (3) 88 ne (3) 88 d2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 d2 - 2 1.00 1.05 1.10 0.039 0.041 0.043 d2 - 3 1.00 1.05 1.10 0.039 0.041 0.043 d2 - 4 1.92 1.97 2.02 0.075 0.077 0.079 e2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 e2 - 2 1.61 1.66 1.71 0.063 0.065 0.067 e2 - 3 1.43 1.48 1.53 0.056 0.058 0.060 ecn: t-08957-rev. a, 29-dec-08 dwg: 5983
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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